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femtoclocks? crystal-to-lvpecl 350mhz frequency margining synthesizer ics843207-350 idt ? / ics ? lvpecl frequency margining synthesizer 1 ics843207by-350 rev. a october 23, 2008 preliminary g eneral d escription the ics843207-350 is a low phase-noise frequency margining synthesizer that targets clocking for high performance interfaces such as spi4.2 and is a member of the hiperclocks? family of high performance clock solutions from idt. in the default mode, the each output can be configured individually to generate an 87.5mhz, 175mhz or 350mhz lvpecl output clock signal from a 14mhz crystal input. there is also a frequency margining mode available where the device can be configured, using control pins, to vary the output frequency up or down from nominal by 5%. the ics843207-350 is provided in a 48-pin lqfp package. f eatures ? seven independently configurable lvpecl outputs at 87.5mhz, 175mhz or 350mhz ? individual tri-state control of each output ? selectable crystal oscillator interface designed for 14mhz, 18pf parallel resonant crystal or lvcmos single-ended input ? output frequency can be varied 5% from nominal ? vco range: 620mhz - 750mhz ? rms phase jitter @ 350mhz, using a 14mhz crystal (12khz - 20mhz): 1.29ps (typical) ? full 3.3v output supply mode ? 0c to 70c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages hiperclocks? ic s b lock d iagram v cca v cc v cco nq6 q6 v ee v cco nq5 q5 nq4 q4 v cco 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 v cco q0 nq0 q1 nq1 v ee v cco q2 nq2 q3 nq3 v cco sel2 sel3 sel4 sel5 sel6 sel7 sel8 sel9 sel10 sel11 sel12 sel13 ics843207-350 48-pin lqfp 7mm x 7mm x 1.4mm package body y package top view sel1 sel0 npll_sel v cc xtal_in xtal_out nxtal_sel ref_clk v ee mr margin mode p in a ssignment 0 1 1 0 phase detector vco 620 - 750mhz 100 (95, 105) osc predivider 2 2 00 hiz 01 2 10 8 11 4 2 00 hiz 01 2 10 8 11 4 2 00 hiz 01 2 10 8 11 4 2 00 hiz 01 2 10 8 11 4 2 00 hiz 01 2 10 8 11 4 2 00 hiz 01 2 10 8 11 4 2 00 hiz 01 2 10 8 11 4 q0 nq0 sel[1:0] q1 nq1 sel[3:2] q2 nq2 sel[5:4] q3 nq3 sel[7:6] q4 nq4 sel[9:8] q5 nq5 sel[11:10] q6 nq6 sel[13:12] pulldown pulldown pulldown pulldown pulldown npll_sel xtal_in xtal_out ref_clk nxtal_sel mode margin mr pulldown 14mhz pullup pullup pullup pullup pullup pullup pullup to o/p dividers the preliminary information presented herein represents a product in pre-production. the noted characteristics are based on ini tial product characterization and/or qualification. integrated device technology, incorporated (idt) reserves the right to change any circuitry or specificat ions without notice.
idt ? / ics ? lvpecl frequency margining synthesizer 2 ics843207by-350 rev. a october 23, 2008 ics843207-350 femtoclocks? crystal-to-lvpecl 350mhz frequency margining synthesizer preliminary f unctional d escription the ics843207-350 features a fully integrated pll and therefore requires no external components for setting the loop bandwidth. a 14mhz fundamental crystal is used as the input to the on chip oscillator. the output of the oscillator is fed into the pre-divider. in frequency margining mode, the 14mhz crystal frequency is divided by 2 and a 7mhz reference frequency is applied to the phase detector. the vco of the pll operates over a range of 620mhz to 800mhz. the output of the m divider is also applied to the phase detector. the default mode for the ics843207-350 is a nominal 350mhz with each output configurable to divide by 1, 2 or 4. the nominal output frequency can be changed by placing the device into the margining mode using the mode pin and using the margin pin to change the m feedback divider. frequency margining mode operation occurs when the mode input is high. the phase detector and the m divider force the vco output frequency to be m times the reference frequency by adjusting the vco control voltage. the output of the vco is scaled by an output divider prior to being sent to the lvpecl output buffer. the divider provides a 50% output duty cycle. the relationship between the crystal input frequency, the m divider, the vco frequency and the output frequency is provided in table 1a. when changing back from frequency margining mode to nominal mode, the device will return to the default nominal configuration described above. t able 1a. f requency s elect f unction t able t able 1b. f requency m argin f unction t able ) z h m ( l a t xx l e s1 - x l e s) z h m ( o c vr e d i v i d t u p t u o) z h m ( y c n e u q e r f t u p t u o 4 100 0 0 7a / nz i h 4 101 0 0 72 0 5 3 4 110 0 0 78 5 . 7 8 4 111 0 0 74 5 7 1 e d o mn i g r a m) z h m ( l a t x) p ( r e d i v i d - e r p e c n e r e f e r ) z h m ( y c n e u q e r f k c a b d e e f r e d i v i d ) z h m ( o c ve g n a h c % 10 4 12 7 5 95 6 60 . 5 - 0x 4 11 4 10 0 10 0 7e d o m . m o n 11 4 12 7 5 0 15 3 70 . 5
idt ? / ics ? lvpecl frequency margining synthesizer 3 ics843207by-350 rev. a october 23, 2008 ics843207-350 femtoclocks? crystal-to-lvpecl 350mhz frequency margining synthesizer preliminary t able 2. p in d escriptions t able 3. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k r p u l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k t able 4a. nxtal_sel c ontrol i nput f unction t able t u p n i l e s _ l a t x ne c r u o s d e t c e l e s 0t u o _ l a t x , n i _ l a t x 1k l c _ f e r t u p n in o i t i d n o c e d o m6 q : 0 q n , 6 q : 0 q 0e d o m t l u a f e d 1e d o m g n i n i g r a m y c n e u q e r f t able 4b. m ode c ontrol i nput f unction t able r e b m u ne m a ne p y tn o i t p i r c s e d , 2 1 , 7 , 1 4 3 , 0 3 , 5 2 v o c c r e w o p. s n i p y l p p u s t u p t u o 3 , 20 q n , 0 qt u p u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 5 , 41 q n , 1 qt u p u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 1 3 , 6 1 , 6v e e r e w o p. s n i p y l p p u s e v i t a g e n 9 , 82 q n , 2 qt u p u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 1 1 , 0 13 q n , 3 qt u p u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 3 1e d o mt u p n in w o d l l u p . e d o m g n i n i g r a m y c n e u q e r f = h g i h . e d o m t l u a f e d = w o l . n i p e d o m . s l e v e l e c a f r e t n i l t t v l / s o m c v l . b 4 e l b a t e e s 4 1n i g r a mt u p n in w o d l l u p . e d o m g n i n i g r a m y c n e u q e r f n i % 5 o t n i g r a m y c n e u q e r f e h t s t e s . s l e v e l e c a f r e t n i l t t v l / s o m c v l . b 1 e l b a t e e s 5 1r mt u p n in w o d l l u p e r a s r e d i v i d l a n r e t n i e h t , h g i h c i g o l n e h w . t e s e r r e t s a m h g i h e v i t c a x q n s t u p t u o d e t r e v n i d n a w o l o g o t x q s t u p t u o e u r t e h t g n i s u a c t e s e r e r a s t u p t u o e h t d n a s r e d i v i d l a n r e t n i e h t , w o l c i g o l n e h w . h g i h o g o t . s l e v e l e c a f r e t n i l t t v l / s o m c v l . d e l b a n e 7 1k l c _ f e rt u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . k c o l c t u p n i e c n e r e f e r 8 1l e s _ l a t x nt u p n in w o d l l u p k c o l c e c n e r e f e r e h t d n a l a t s y r c e h t n e e w t e b s t c e l e s . n i p t c e l e s l a t s y r c . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s t u p n i , 9 1 0 2 , t u o _ l a t x n i _ l a t x t u p n i , t u p t u o e h t s i t u o _ l a t x . e c a f r e t n i l a t s y r c t n a n o s e r l e l l a r a p . t u p n i e h t s i n i _ l a t x 5 3 , 1 2v c c r e w o p. s n i p y l p p u s e r o c 2 2l e s _ l l p nt u p n in w o d l l u p y l t c e r i d d e f s i t u p n i d n a d e s s a p y b s i l l p , h g i h n e h w . n i p t c e l e s l l p . d e l b a n e s i l l p , w o l n e h w . s r e d i v i d t u p t u o e h t o t . s l e v e l e c a f r e t n i l t t v l / s o m c v l , 4 2 , 3 2 , 8 3 , 7 3 , 0 4 , 9 3 , 2 4 , 1 4 , 4 4 , 3 4 , 6 4 , 5 4 8 4 , 7 4 , 1 l e s , 0 l e s , 3 l e s , 2 l e s , 5 l e s , 4 l e s , 7 l e s , 6 l e s , 9 l e s , 8 l e s , 1 1 l e s , 0 1 l e s 3 1 l e s , 2 1 l e s t u p n ip u l l u p . a 1 e l b a t e e s . s n i p t c e l e s r e d i v i d t u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l 7 2 , 6 24 q n , 4 qt u p u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 9 2 , 8 25 q n , 5 qt u p u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 3 3 , 2 36 q n , 6 qt u p u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 6 3v a c c r e w o p. n i p y l p p u s g o l a n a : e t o n n w o d l l u p d n a p u l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r number name type description
idt ? / ics ? lvpecl frequency margining synthesizer 4 ics843207by-350 rev. a october 23, 2008 ics843207-350 femtoclocks? crystal-to-lvpecl 350mhz frequency margining synthesizer preliminary t able 5a. p ower s upply dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o contin uous current 50ma surge current 100ma package thermal impedance, ja 47.9c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional op- eration of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a c c e g a t l o v y l p p u s g o l a n av c c 5 1 . 0 ?3 . 3v c c v v o c c e g a t l o v y l p p u s t u p t u o 5 3 1 . 33 . 35 6 4 . 3v i e e t n e r r u c y l p p u s r e w o p 0 2 2a m i a c c t n e r r u c y l p p u s g o l a n a 5 1a m t able 5b. lvcmos / lvttl dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n iv c c v 3 . 3 =2v c c 3 . 0 +v v l i e g a t l o v w o l t u p n iv c c v 3 . 3 =3 . 0 -8 . 0v i h i t u p n i t n e r r u c h g i h , n i g r a m , k l c _ f e r , l e s _ l l p n , e d o m l e s _ l a t x n , r m v c c v = n i 5 6 4 . 3 =0 5 1a 3 1 l e s : 0 l e sv c c v = n i 5 6 4 . 3 =5a i l i t u p n i t n e r r u c w o l , n i g r a m , k l c _ f e r , l e s _ l l p n , e d o m l e s _ l a t x n , r m v c c , v 5 6 4 . 3 = v n i v 0 = 5 -a 3 1 l e s : 0 l e s v c c , v 5 6 4 . 3 = v n i v 0 = 0 5 1 -a / t v n o i t s i s n a r t t u p n i e t a r l l a f / e s i r e d o m , 3 1 l e s : 0 l e s 0 2v / s n
idt ? / ics ? lvpecl frequency margining synthesizer 5 ics843207by-350 rev. a october 23, 2008 ics843207-350 femtoclocks? crystal-to-lvpecl 350mhz frequency margining synthesizer preliminary t able 6. c rystal c haracteristics t able 5c. lvpecl dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov o c c 4 . 1 -v o c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov o c c 0 . 2 -v o c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p 6 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t o c c . v 2 - r e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n o i t a l l i c s o f o e d o m l a t n e m a d n u f y c n e u q e r f 4 1z h m ) r s e ( e c n a t s i s e r s e i r e s t n e l a v i u q e 0 4 e c n a t i c a p a c t n u h s 7f p l e v e l e v i r d 0 0 3w . l a t s y r c t n a n o s e r l e l l a r a p f p 8 1 n a g n i s u d e z i r e t c a r a h c : e t o n t able 7. i nput f requency c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f n i t u p n i y c n e u q e r f k l c _ f e r4 . 2 14 15 1z h m t u o _ l a t x / n i _ l a t x4 . 2 14 15 1z h m t able 8. ac c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 2 = n0 1 30 5 35 7 3z h m 4 = n5 5 15 7 15 . 7 8 1z h m 8 = n5 . 7 75 . 7 85 7 . 3 9z h m t ) ? ( t i j , r e t t i j e s a h p s m r 1 e t o n ; m o d n a r w o l = e d o m ) z h m 0 2 - z h k 2 1 ( , z h m 0 5 3 9 2 . 1s p w o l = e d o m ) z h m 0 2 - z h k 2 1 ( , z h m 5 7 1 4 3 . 1s p w o l = e d o m ) z h m 0 2 - z h k 2 1 ( , z h m 5 . 7 8 6 4 . 1s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 25 2 4s p c d oe l c y c y t u d t u p t u o 0 5% . l a t s y r c z h m 4 1 a g n i s u d e z i r e t c a r a h c : 1 e t o n
idt ? / ics ? lvpecl frequency margining synthesizer 6 ics843207by-350 rev. a october 23, 2008 ics843207-350 femtoclocks? crystal-to-lvpecl 350mhz frequency margining synthesizer preliminary o ffset f requency (h z ) dbc hz n oise p ower t ypical p hase n oise at 350mh z 350mhz rms phase noise jitter 12khz to 20mhz = 1.29ps (typical) o ffset f requency (h z ) dbc hz n oise p ower t ypical p hase n oise at 175mh z 175mhz rms phase noise jitter 12khz to 20mhz = 1.34ps (typical) ? ? ? ? ? ? phase noise result by adding 10 gigabit ethernet filter to raw data raw phase noise data 10 gigabit ethernet filter 10 gigabit ethernet filter raw phase noise data phase noise result by adding 10 gigabit ethernet filter to raw data
idt ? / ics ? lvpecl frequency margining synthesizer 7 ics843207by-350 rev. a october 23, 2008 ics843207-350 femtoclocks? crystal-to-lvpecl 350mhz frequency margining synthesizer preliminary p arameter m easurement i nformation t pw t period t pw t period odc = x 100% q0:q6 o utput d uty c ycle /p ulse w idth /p eriod rms p hase j itter 3.3v c ore /3.3v o utput l oad ac t est c ircuit o utput r ise /f all t ime clock outputs 20% 80% 80% 20% t r t f v sw i n g nq0:nq6 phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power scope qx nqx lvpecl v ee 2v -1.3v 0.165v 2v v cc , v cco v cca
idt ? / ics ? lvpecl frequency margining synthesizer 8 ics843207by-350 rev. a october 23, 2008 ics843207-350 femtoclocks? crystal-to-lvpecl 350mhz frequency margining synthesizer preliminary a pplication i nformation c rystal i nput i nterface the ics843207-350 has been characterized with 18pf parallel resonant crystals. the capacitor values shown in f igure 2. c rystal i npu t i nterface figure 2 below were determined using a 14mhz, 18pf parallel resonant crystal and were chosen to minimize the ppm error. as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ics843207-350 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc , v cca , and v cco should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 1 illustrates how a 10 resistor along with a 10f and a 0.01 f bypass capacitor should be connected to each v cca . p ower s upply f iltering t echniques f igure 1. p ower s upply f iltering 10 v cca 10 f .01 f 3.3v .01 f v cc c1 27p x1 18pf parallel crystal c2 27p xtal_out xtal_in
idt ? / ics ? lvpecl frequency margining synthesizer 9 ics843207by-350 rev. a october 23, 2008 ics843207-350 femtoclocks? crystal-to-lvpecl 350mhz frequency margining synthesizer preliminary i nputs : c rystal i nput for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k resistor can be tied from xtal_in to ground. ref_clk i nput for applications not requiring the use of the reference clock, it can be left floating. though not required, but for additional protection, a 1k resistor can be tied from the ref_clk to ground. lvcmos c ontrol p ins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvpecl o utputs all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. lvcmos to xtal i nterface the xtal_in input can accept a single-ended lvcmos signal through an ac couple capacitor. a general interface diagram is shown in figure 3. the xtal_out pin can be left floating. the input edge rate can be as slow as 10ns. for lvcmos inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. this configuration requires that the output f igure 3. g eneral d iagram for lvcmos d river to xtal i nput i nterface impedance of the driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 applications, r1 and r2 can be 100 . this can also be accomplished by removing r1 and making r2 50 . r2 zo = 50 vdd ro zo = ro + rs r1 vdd xta l _ i n xta l _ o u t .1uf rs
idt ? / ics ? lvpecl frequency margining synthesizer 10 ics843207by-350 rev. a october 23, 2008 ics843207-350 femtoclocks? crystal-to-lvpecl 350mhz frequency margining synthesizer preliminary t ermination for 3.3v lvpecl o utput v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin the clock layout topology shown below is a typical termina- tion for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, ter- minating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are f igure 4b. lvpecl o utput t ermination f igure 4a. lvpecl o utput t ermination designed to drive 50 transmission lines. matched imped- ance techniques should be used to maximize operating fre- quency and minimize signal distortion. figures 4a and 4b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
idt ? / ics ? lvpecl frequency margining synthesizer 11 ics843207by-350 rev. a october 23, 2008 ics843207-350 femtoclocks? crystal-to-lvpecl 350mhz frequency margining synthesizer preliminary p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics843207-350. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics843207-350 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 220ma = 762.3mw ? power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 7 * 30mw = 210mw total power _max (3.63v, with all outputs switching) = 762.3mw + 210mw = 972.3mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1c/w per table 9 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.972w *42.1c/w = 110.9c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67.8c/w 55.9c/w 50.1c/w multi-layer pcb, jedec standard test boards 47.9c/w 42.1c/w 39.4c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 9. t hermal r esistance ja for 48-p in lqfp, f orced c onvection
idt ? / ics ? lvpecl frequency margining synthesizer 12 ics843207by-350 rev. a october 23, 2008 ics843207-350 femtoclocks? crystal-to-lvpecl 350mhz frequency margining synthesizer preliminary 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 5. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cco - 2v. ? for logic high, v out = v oh_max = v cco_max ? 0.9v (v cco_max - v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cco_max ? 1.7v (v cco_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max - 2v))/r l ] * (v cco_max - v oh_max ) = [(2v - (v cco_max - v oh_max )) /r l ] * (v cco_max - v oh_max ) = [(2v - 0.9v)/50 ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cco_max - 2v))/r l ] * (v cco_max - v ol_max ) = [(2v - (v cco_max - v ol_max )) /r l ] * (v cco_max - v ol_max ) = [(2v - 1.7v)/50 ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 5. lvpecl d river c ircuit and t ermination q1 v out v cco rl 50 v cco - 2v
idt ? / ics ? lvpecl frequency margining synthesizer 13 ics843207by-350 rev. a october 23, 2008 ics843207-350 femtoclocks? crystal-to-lvpecl 350mhz frequency margining synthesizer preliminary r eliability i nformation t ransistor c ount the transistor count for ics843207-350 is: 4380 t able 10. ja vs . a ir f low t able for 48 l ead lqfp ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67.8c/w 55.9c/w 50.1c/w multi-layer pcb, jedec standard test boards 47.9c/w 42.1c/w 39.4c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
idt ? / ics ? lvpecl frequency margining synthesizer 14 ics843207by-350 rev. a october 23, 2008 ics843207-350 femtoclocks? crystal-to-lvpecl 350mhz frequency margining synthesizer preliminary p ackage o utline - y s uffix for 48 l ead lqfp t able 11. p ackage d imensions reference document: jedec publication 95, ms-026 n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s c b b m u m i n i ml a n i m o nm u m i x a m n 8 4 a - -- -0 6 . 1 1 a 5 0 . 0- -5 1 . 0 2 a 5 3 . 10 4 . 15 4 . 1 b 7 1 . 02 2 . 07 2 . 0 c 9 0 . 0- -0 2 . 0 d c i s a b 0 0 . 9 1 d c i s a b 0 0 . 7 2 d . f e r 0 5 . 5 e c i s a b 0 0 . 9 1 e c i s a b 0 0 . 7 2 e . f e r 0 5 . 5 e c i s a b 0 5 . 0 l 5 4 . 00 6 . 05 7 . 0 0 - - 7 c c c - -- -8 0 . 0
idt ? / ics ? lvpecl frequency margining synthesizer 15 i cs843207by-350 rev. a october 23, 2008 ics843207-350 femtoclocks? crystal-to-lvpecl 350mhz frequency margining synthesizer preliminary t able 12. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t 0 5 3 - y b 7 0 2 3 4 8 0 53b7023 4p fqldael8 4y ar tc 07otc0 t 0 5 3 - y b 7 0 2 3 4 8 0 53b7023 4p fqldael8 4l eer&epat000 1c 07otc0 f l 0 5 3 - y b 7 0 2 3 4 8 l 053b702 3p fql"eerf-dael"dael8 4y ar tc 07o tc0 t f l 0 5 3 - y b 7 0 2 3 4 8 l 053b702 3p fql"eerf-dael"dael8 4l eer&epat000 1c 07otc0 . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature ranges, high reliability or other extraordina ry environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or w arrant any idt product for use in life support devices or critical medical instruments.
innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 corporate headquarters integrated device t echnology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 fax: +44 (0) 1372 378851 ics843207-350 femtoclocks? crystal-to-lvpecl 350mhz frequency margining synthesizer preliminary ? 2007 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, the idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa

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